We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39184

Spartan-6 - Is it possible to drive PLLs in the top and bottom of the device using an IBUFGDS or IBUFG?


I want to drive PLLs in the top and bottom of a device. Is it possible to use an IBUFGDS or IBUFG?


The IBUFGDS and IBUFG have dedicated connections to their "Local" CMTs (PLLand 2 DCMs).Driving PLLs or DCMs in boththe top and bottom of the deviceusing the IBUFGDS or IBUFG results in routing errors because they are limited to where they can route to on the Global Clock Network.

Using the above setup could lead to the following PLACE error:

"ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK_p> is placed at site <PAD101>. The BUFIO component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0> is placed at site <BUFIO2_X4Y20>."

ABUFG should be used for routing from a GCLK pin to multiple CMTs, or to reach the top and bottom of the device.



Answer Number 问答标题 问题版本 已解决问题的版本
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 39184
日期 12/15/2012
状态 Active
Type 综合文章