AR# 39353: Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2
Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2
This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.2 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.
VHDL source code generation now supported. Also includes Example Design, testbench and simulation and implementation scripts.
8-lane Gen2 Endpoint Configuration in a -2 Speed Grade device
The 8-lane Gen2 Endpoint Configuration, in a -2 Speed Grade device, has been restricted to "High" performance Level, as the "Good" Performance Level block RAM cannot be run at 500 MHz as required for this configuration.
INTERRUPT_PIN attribute update based on Legacy Interrupt option in GUI
Issue resolved where Unchecking the Legacy Interrupt option was not updating the INTERRUPT_PIN attribute.
Timing path ignored in Flat flow but analyzed in Hierarchical flow
Timing improvement for 8-lane Gen2 Configuration : Timing Ignore (TIG) added to sel_lnk_rate path. This path was being analyzed in hierarchical flow causing failure to meet timing.
Resolved Issues 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723. 02/14/2011 - Added 39456 and 40637. 01/03/2011 - Added the general information, new features section, and device support. 12/24/2010 - Initial Release