We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3938

F1.4, F1.5, Timing Simulator: '-' in signal names converted to '_'


Keywords: Foundation, ngd2edif, simulation, -, _,

Urgency: Standard

General Description:
When a design contains a dash as the last character in a signal name ('-'), the dash
is converted to an underscore by ngd2edif when doing a backannotate (timing sim).

In timing simulation, this will cause test vectors created in Functional simulation to
appear blank (or missing signals), as well as problems with command files in
simulation, that refer to specific signal names, due to the fact that the names have
been changed from containing '-' to containing '_'.

This renaming can be seen in the time_sim.edn file.


Remove any dashes ('-') from the end of names in the design, or replace them with
AR# 3938
日期 03/06/2002
状态 Archive
Type 综合文章