AR# 39423

MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade

描述

In some instances, MIG will place an I/O on VRN/VRP pins in a bank even if very few data signals are used on that bank and there are many other available I/O.

If Internal VREF is disabled, then this bank must be used as a Slave Bank for DCI Cascading, which can limit the bank usage for the remaining available I/O.

解决方案

If this placement is not desired, you can generate the MIG design using the default pinout and manually modify the generated *.ucf constraint file.

Then, run the MIG generated mig.prj and the modified *.ucf through the "Verify UCF and Update Design and UCF" flow in the MIG GUI.

This will validate your pinout changes and regenerates the MIG design according to your new pinout.

For more details on when VRP/VRN can be used as GPIO, refer to (Xilinx Answer 38926).

This behavior is scheduled to be changed starting in ISE 14.1 software.

链接问答记录

主要问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
39843 13.x EDK - Master Answer Record N/A N/A

相关答复记录

AR# 39423
日期 08/18/2014
状态 Active
Type 已知问题
器件 More Less
IP