AR# 39548: Spartan-6 FPGA Integrated Block for PCI Express - Replay Timeout is occuring too fast when using VHDL wrapper
AR# 39548
Spartan-6 FPGA Integrated Block for PCI Express - Replay Timeout is occuring too fast when using VHDL wrapper
描述
Version Found: 1.1; v2.1 Version Resolved and other Known Issues: See (Xilinx Answer 45702).
When targeting VHDL, the replay timer expires too fast which causes link problems.
解决方案
For the Spartan-6 FPGA Integrated Block, if you are using VHDL of the core, the Replay Timeout value is set incorrectly in the example file provided with the wrapper causing the timer countdown to count at a rate faster than expected.
To correct this problem, edit the "xilinx_pcie_1_1_ep_s6.vhd" file found in the generated core's example_design directory and make the following changes:
Revision History 01/18/2012 - Updated; added reference to 45072 12/24/2010 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.