AR# 39649

描述

解决方案

Some XST constraints can beapplied not only globally but also specifically tocertain modules,instances or signals within the RTL code. Followingisa general description of the constraints syntax applied in RTL code.

• VHDL

Constraints can be specified in VHDL code with VHDL attributes. It consists of two parts, attributes declaration and attributes specification.

attribute constraint_name : string;

attribute constraint_name of object_name :{component|label|entity|signal|variable} is constraint_value;

Examples:

Entity example1 is

port (......);

attributekeep_hierarchy string;

attributekeep_hierarchyofexample1 : entity isyes;

end example1;

architecturearch1 ofexample1 is

......

attribute keep string;

attributekeepofsignal1 :signal istrue;

attribute keep_hierarchy of component1 : component is yes;

begin
......

end arch1;

• Verilog

Verilog attributes are bounded by brackets and asterisks.

(* attribute_name = "attribute_value" *)

Examples:

(*keep_hierarchy = "yes"*)

module top (......);

......

(*keep = "true"*) reg [1:0] a_reg;

......

endmodule

For more informationabout any XST constraints syntax in RTL code, please refer to UG627/687-XST User Guide (Xilinx Answer 38931).

For more information of Constraints entry method in VHDL and Verilog code, please refer to "Chapter 2-Entry Strategies for Xilinx Constraints" in UG625-Constraints Guide.

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