UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3965

V1.5, V1.4.0 CORE Generator - COREGen may create VHX, XNF(v1.4)/EDN(v1.5) and XSF output files when not directed to do so.

Description

Keywords: CORE Generator, COREGen, extra, extraneous, file, VHX, XNF, XSF

Urgency: Standard

General Description:
CORE Generator may create VHX, XNF (or EDN) and XSF output files,
even when not directed to do so.

解决方案

Selecting the "XNF Implementation Netlist" (v1.4 only), "Edif
Implementation Netlist (v1.5), "VHDL Instantiation Template",
"Verilog Instantiation Template" or "Viewlogic Schematic
Symbol" output format option all result in outputs that
include .VHX files.

Also, selecting the "VHDL Instantiation Template", "Verilog
Instantiation Template" or "Viewlogic Schematic Symbol"
setting all result in both a .XNF (v1.4 only) or .EDN (v1.5
only) and a .XSF file being produced, even though these were
not requested by the user.

These files should only be produced when the XNF (v1.4 only) or Edif Implementation Netlist option is selected.

These files are extraneous and can be ignored.
AR# 3965
创建日期 05/21/1998
Last Updated 02/11/2001
状态 Archive
Type 综合文章