This solution record shows how to manually instantiate I/O cells in VHDL.
FPGA Express 2.x and older can insert all of the I/O in a design or none at all, so if any I/O are instiated in a design, all of the I/O must be instantiated.
FPGA Express 3.x can insert unspecified I/O; you can instantiate some of the I/O and let Express insert the rest.
解决方案
1
Input signals
1. IBUF
-- IBUF declaration component IBUF port(I: in STD_LOGIC; O: out STD_LOGIC); end component;
-- IBUF instantiation U1: IBUF port map (I => INPUTSIG_PI, O => INPUTSIG);
INPUTSIG can be connected to internal logic. The following can be used in a UCF file to lock the pin. NET INPUTSIG_PI LOC=Pxx;
2. IFD
-- IFD declaration component IFD port(D: in STD_LOGIC; C: in STD_LOGIC; Q: out STD_LOGIC); end component;
-- IFD instantiation U2: IFD port map (D => DATAIN_PI, C => CLK, Q => DATAIN_R);
DATAIN_R can be connected to internal logic. The following can be used in a UCF file to lock the pin. NET DATAIN_PI LOC=Pxx;
2
Output signals
1. OBUF
-- OBUF declaration component OBUF port(I: in STD_LOGIC; O: out STD_LOGIC); end component;
-- OBUF instantiation U3: OBUF port map (I => OUTPUTSIG, O => OUTPUTSIG_PO);
OUTPUTSIG can be connected to internal logic. The following can be used in a UCF file to lock the pin. NET OUTPUTSIG_PO LOC=Pxx;
2. OFD
-- OFD declaration component OFD port(D: in STD_LOGIC; C: in STD_LOGIC; Q: out STD_LOGIC); end component;
-- OFD instantiation U4: OFD port map (D => DATAOUT, C => CLK, Q => DATAOUT_PO);
DATAOUT can be connected to internal logic. The following can be used in a UCF file to lock the pin. NET DATAOUT_PO LOC=Pxx;
2. OBUFT
-- OBUFT declaration component OBUFT port(I: in STD_LOGIC; T: in STD_LOGIC; O: out STD_LOGIC); end component;
-- OBUFT instantiation U5: OBUFT port map (I => DATAOUT, T => CONTROL, O => DATAOUT_PO);
DATAOUT can be connected to internal logic.
Note: The OBUFE macro cannot be instantiated. The signal connected to the T control pin must be inverted to act as an OBUFE.
3
Clock signals
1. BUFG This example shows how to instantiate a global buffer being driven directly by an input signal. This involves a modification to the resulting XNF netlist because a global buffer can be driven by an internal node as well as by an external input signal. This resolution applies only to designs where all the I/O components are instantiated by the user and I/O pads have NOT be inserted by FPGA Express.
(If directly driving the global buffer is not desired, and having the signal go through an IBUF then a BUFG is wanted instead, the previous IBUF example can be used followed by instantiating a BUFG, and there is no need to modify the XNF.)
-- BUFG declaration component BUFG port(I: in STD_LOGIC; O: out STD_LOGIC); end component;
-- BUFG instantiation U6: BUFG port map (I => CLK_PI, O => CLK);
In the XNF netlist, the following line will appear towards the end of the file. SIG, CLK_PI, PIN=CLK_PI Replace this line with the following. EXT, CLK_PI, I
CLK can be connected to internal logic. The following can be used in a UCF file to lock the pin to a clock IOB. NET CLK_PI LOC=Pxx;