general description: If a HDL design contains bidiretional IO, sometimes FPGA Compiler will be unable to infer the correct type of IO; insert_pads sometimes fails. This happens if IOB_4000 are left in the netlist, or insert_pads/compile reports an error like this:
Error: Need to insert a pad on port 'MYCLOCK' before compiling. (OPT-1000)
This solution has tips on handling problems when insert_pads fails. This solution record applies to both FPGA Compiler and Design Compiler. This solution applies to any family in the FPGA Compiler/Design Compiler flow that uses the insert_pads/set_port_is_pads commands.
解决方案
FPGA Compiler is capable of inferring input buffers, output buffers, and non-registered bidirectional I/O. With the XC4000X IOB structure, there are input and output registers that can be used in input, output, and bidirectional I/O. Certain types of I/Os or coding styles require special handling in FPGA Compiler such as if an I/O port uses IOB registers and/or the HDL code tri-state behavior is not in the top-level HDL file.
In general, FPGA Compiler can infer simple I/O. Simple I/O is defined as a top-level port which requires an input buffer, output buffer, output tri-state, input register, or output register. If a designer wants to use an input or output register for a top-level port, the HDL that infers the register must not describe an asynchronous set or asynchronous reset. The XC4000X I/O FFs do not have an asynchronous set or asynchronous reset a designer can toggle. Additionally, a bidirectional pin which uses only an input buffer and tri-stateable output buffer is also a simple I/O.
To infer simple bidirectional I/O using FPGA Compiler, the HDL that describes this type of I/O must reside in the top-level HDL. If the I/O is not described at the top-level HDL, typically an abnormal termination for insert_pads will be reported, and/or FPGA Compiler will write out an IOB_4000 cell into the Xilinx .SXNF file. In the Xilinx place and route environment, the presence of an IOB_4000 cell will create an unexpanded block error from ngdbuild and M1 will not process the design.
For both Verilog and VHDL, a conditional assignment statement which shares a common port with a continuous assignment statement will infer a simple bidirectional I/O, a bidirectional pin composed of an IBUF and an OBUFT.
For Verilog, a simple bidirectional pin would be described as:
For VHDL, a simple bidirectional pin would be described as
entity top is port(A: inout STD_LOGIC; B: in STD_LOGIC,...); end top; architecture inside of top is . . begin
internal_sig <= A; process begin if(control == 1) then A<=output_sig; else A<=z; end if; end process; . .
end inside;
For both Verilog and VHDL, the HDL code that describes the input path, output path, and control signal were at the top-level. If one or more of the three mentioned HDL structures is instead in a lower-level of hierarchy, FPGA Compiler may not be able to infer the simple bidirectional I/O. If it is not possible to move the entire behavior of the simple bidirectional I/O to the top-level HDL, the following compile strategies can be tried (Sometimes using one or more of the following suggestions together can produce a workable solution):
(a) instead of executing set_port_is_pad/insert_pads before compile, execute these commands after compile.
(b) instead of executing the set_port_is_pad/insert_pads command after compile, execute these commands before compile.
(c) Run the insert_pads command with the -thru_hierarchy option.
(d) Flatten the design using compile -ungroup_all, and then follow up compile with set_port_is_pad and inset_pads commands.
(e) On the bidirectional ports that are not successfully replacing the IOB_4000 cells with the proper IBUF/OBUFT combination, instantiate the IBUF/OBUFT cells and do not place a port_is_pad attribute on that port.
(f) Try using the latest version of FPGA Compiler/Design Compiler.
Any type of bidirectional I/O that uses an IOB register, an IOB register with an IOB tri-state, and/or uses a registered and non-registered version of an input/output signal, cannot be inferred via FPGA Compiler. FPGA Express does not have this limitation. If using FPGA Express is not an option, the best way to handle complex I/Os mentioned is to instantiate the cells. For the names of I/O cells and their pins, refer to Appendix A of the XSI User Guide.