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AR# 39960

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC - Synopsys VCS back-annotated timing simulations time out

描述

Using the Synopsys VCS simulator to perform back-annotated timing simulations of certain configurations of the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC can result in the following error:

ERROR - Testbench timed out

Specifically, the TEMAC_SINGLE SecureIP model's EMACPHYTXGMIIMIICLKOUT clock output fails to toggle in some cases, resulting in a lack of transmitter operation. 

This is due to pulse-swallowing of the PHYEMACGTXCLK input within the X_TEMAC_SINGLE simprim instance, and is limited to timing simulations when using the Synopsys VCS simulator.

This issue has been seen with the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.5 and v2.1 wrappers in ISE 12.x and ISE 13.x.

解决方案

To work around this problem, use another supported simulator to perform back-annotated timing simulations.

Alternatively, if use of the Synopsys VCS simulator is desired, you can do one of the following:

  • Address pulse swallowing behavior according to (Xilinx Answer 9872)
     
  • Remove SDF timing data back-annotation by removing the "-sdf" argument from the vcs command (for example in the provided simulate_vcs.sh script)

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40633 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.5 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 39960
日期 09/08/2014
状态 Active
Type 综合文章
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper
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