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AR# 3999

FPGA Express - Instantiating I/O in Verilog.

Description

Keywords: FPGA Express, instantiate, I/O, IBUF, OBUF, BUFG.

Urgency: Standard

General Description:
This Answer Record explains how to manually instantiate I/O cells in Verilog.

FPGA Express 2.x and older can insert either all of the I/O in a design or none at all; therefore, if any I/O are instantiated in a design, all of the I/O must be instantiated.

FPGA Express 3.x can insert unspecified I/O; you can instantiate some of the I/O and let FPGA Express insert the rest.

解决方案

1

Input signals

1. IBUF

// IBUF instantiation
IBUF INPUTSIG_IBUF (.I(INPUTSIG_PI), .O(INPUTSIG));

INPUTSIG can be connected to internal logic. Use the following in a UCF file to lock the pin:
NET INPUTSIG_PI LOC=Pxx;

2. IFD

// IFD instantiation
IFD DATAIN_IFD (.D(DATAIN_PI), .C(CLK), .Q(DATAIN_R));

DATAIN_R can be connected to internal logic. Use the following in a UCF file to lock the pin:
NET DATAIN_PI LOC=Pxx;

2

Clock signals

1. BUFG
This example illustrates how to instantiate a global buffer being driven directly by an input signal. This involves a modification to the resulting XNF netlist because a global buffer can be driven by an internal node, as well as by an external input signal.

(If you do not wish to directly drive the global buffer, and would rather have the signal go through an IBUF, then a BUFG, you can use the previous IBUF example followed by the instantiation of a BUFG, and there is no need to modify the XNF.)

// BUFG instantiation
BUFG CLK_BUFG (.I(CLK_PI), .O(CLK));

In the XNF netlist, the following line will appear towards the end of the file:
SIG, CLK_PI, PIN=CLK_PI

Replace this with the following:
EXT, CLK_PI, I

CLK can be connected to internal logic. Use the following in a UCF file to lock the pin to a clock IOB:
NET CLK_PI LOC=Pxx;

3

Output signals

1. OBUF

// OBUF instantiation
OBUF OUTPUTSIG_OBUF (.I(OUTPUTSIG), .O(OUTPUTSIG_PO));

OUTPUTSIG can be connected to internal logic. Use the following in a UCF file to lock the pin:
NET OUTPUTSIG_PO LOC=Pxx;

2. OFD

// OFD instantiation
OFD DATAOUT_OFD (.D(DATAOUT), .C(CLK), .Q(DATAOUT_PO));

DATAOUT can be connected to internal logic. Use the following in a UCF file to lock the pin:
NET DATAOUT_PO LOC=Pxx;

3. OBUFT

// OBUFT instantiation
OBUFT DATAOUT_OBUFT (.I(DATAOUT), .T(CONTROL), .O(DATAOUT_PO));

DATAOUT can be connected to internal logic.

(NOTE: The OBUFE macro cannot be instantiated. The signal connected to the T control pin must be inverted to act as an OBUFE.)
AR# 3999
创建日期 05/29/1998
Last Updated 08/11/2003
状态 Archive
Type 综合文章