The LogiCORE OBSAI IP bypasses both the TX and RX buffers to ensure deterministic latency through the data path. The Virtex-6 GTX Delay Aligner errata item described in (Xilinx Answer 39430) affects the LogiCORE OBSAI IP. Refer to the errata EN142 and product change notice PCN11009 for more information.
Designs using theOBSAI IP need to bypass the TX and RX buffer and need to implement the workaround below in order to ensure deterministic latency through the data path.
Follow the steps below to work around this problem
Step 1 Part of the requirement to fix the Delay Aligner issue is that the GTXTXOUTCLK must drive the MMCM directly with no BUFG in the path. By default, in the wrapper, TXOUTCLK includes a BUFG which must be removed by changing the following lines of code in gtx_and_clocks.vhd:
-- DRP dclk => aux_clk, daddr => mmcm_drp_daddr, den => mmcm_drp_den, di => mmcm_drp_di, dwe => mmcm_drp_dwe, drdy => mmcm_drp_drdy, do => mmcm_drp_do,
usrclk2 => txusrclk2, clk_ok => tx_clk_ok );
Step 2 Ensure the MMCM is located in the region with the MGT providing TXOUTCLK.
One of the requirement to fix the Delay Aligner issue is that the GTX RXUSRCLK2 must be driven by BUFR which itself is driven by the GTX output clock. By default, in the wrapper, RXUSRCLK2 is already driven by the BUFR.
To disable both the Tx Delay Aligner and Rx Delay Aligner make the following changes.
Step 1 In the instantiation of gtx0_gtx_wrapper_i in the file gtx_wrapper.vhd change the Generic GTX_POWER_SAVE from "0000000100" to "0000110100".
Modifying the POWER_SAVE attribute will result in software DRC errors in ISE 12.4, 12.3 and 12.2. These same errors occur in simulation as well. (Xilinx Answer 39434) provides a method for working around these errors.
In gtx_and_clocks.vhd disable the Tx Delay Aligner by changing the following lines of code.
-- Rx Delay Aligner reset held until Rx Phase Align completes -- (and always held reset at lowest 2 line rates where it is not required) aligner_reset <= '1' when (rx_sync_done = '0') or (speed_select(1 downto 0) /= "00") else '0';
aligner_reset <= '1';
Step 5 Tie off aligner_lock:
-- Aligner lock term is needed at higher line rates when Aligner is used aligner_lock_i <= '1' when (speed_select(1 downto 0) /= "00") else aligner_lock;
aligner_lock_i <= '1';
To ensure the MMCM is used to compensate for the BUFG delay correctly the MMCM internal dividers need to be used. Therefore the clocking structure as outlined in AR 39430 can not be used for the OBSAI IP. It is necessary to use clkout0 to drive the userclk and use a second BUFG to the clkfbout pin and feed the output of the second BUFG to the clkfbin pin input of the MMCM.
Step 6 Add a signal clkfbout:
signal clkfbout : std_logic;
Step 7 Add a BUFG to clkfb:
clkfb_bufg : bufg port map ( I => clkfbout, O => clkfb);
Step 8 And on the instantiation of pll_i : MMCM_ADV change: