AR# 40010: FIFO Generator v6.1 - FIFO core should be able to get back to work after it detects both Full and Empty asserted
FIFO Generator v6.1 - FIFO core should be able to get back to work after it detects both Full and Empty asserted
FIFO core should be able to get back to work after it detects both Empty and Full asserted. In this case, FIFO core should also provide a signal showing how much data is still valid the memory after it gets back to work.
The issue is that when the clock has a glitch the FIFO may go into a state where all its internal registers and counts become unpredictable, both full and empty flags get asserted and the probablity of the datacount being uncertain is high. The FIFO is not able to recover when normal is provided later. The solution involves identifying this condition and resetting the FIFO without any external control, and probably also providing an option to enable this feature.
As per the user guide, clocks should be free running. If FULL flag reset value is set to 1, then both EMPTY and FULL will be high.
This is not an issue/bug if the core is used as per recommendations.
The core is not tested for such an environment. This issue will be taken care of in an upcoming release. It is recommended to use a free running clock.