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AR# 40021

CPRI v8.5 - What is the Ethernet Interface FIFO depth and width?

描述

What is the Ethernet Interface FIFO depth and width?

解决方案

Transmitter FIFO is 8192 by 6-bits for MII cores (4-bits data, 1-bit error, 1-bit end-of-frame) and 4096 by 12-bits for GMII cores (8-bits data, 2-bits each for error and end-of-frame).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54473 LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 40021
日期 03/14/2017
状态 Active
Type 综合文章
IP
  • CPRI
的页面