The MIG 7 Series Release Notes and Known Issues have been combined into a single answer record for ease of viewing. Please visit (Xilinx Answer 45195).
This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) 7 Series v1.1 released in ISE Design Suite 13.1 and contains the following information:For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
General Information
For a list of supported memory interfaces and features for 7 Series FPGAs, see:
For a list of supported frequencies for 7 Series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the 7 Series Documentation Center.
The MIG tool includes the appropriate frequency range for specific memory interface configuration outside of this known issue:
(Xilinx Answer 40876) MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications
For information regarding MIG cores for other FPGAs, see the IP Release Notes Guide (XTP025) to locate the appropriate MIG Release Notes and Known Issues Answer Record.
For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.
Pin-Out Information
The MIG 7 Series tool allows users to select specific Byte Groups within an FPGA Bank for Data and Address/Control groups.
The tool does not allow users to select the specific pins within those byte groups.
For more information on moving pins within byte groups, (Xilinx Answer 40428) MIG 7 Series v1.1 - Guidelines for moving pins within a selected byte group
Software Requirements
Known Issues
DDR3 SDRAM Memory Interface Designs
(Xilinx Answer 41981) MIG 7 Series v1.1 DDR3 SDRAM - Addr/Cntrl pins should be limited to a single bank
(Xilinx Answer 40876) MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications
(Xilinx Answer 40426) MIG 7 Series v1.1 - Unrequested Reads are seen in simulation immediately after calibration completes
(Xilinx Answer 40451) MIG 7 Series v1.1 - tIH violations on ODT and CKE are output by the memory simulation model
(Xilinx Answer 40452) MIG 7 Series v1.1 - Memory interface should not span both High Range (HR) and High Performance (HP) banks
(Xilinx Answer 40453) MIG 7 Series v1.1 - Can clk_ref_i, sys_rst, and status signals be located in memory banks (Data and/or Address/Control banks)?
(Xilinx Answer 41244) MIG 7 Series 1.1 - Selected device is not supported by MIG version 1.1
(Xilinx Answer 42320) MIG v3.7 Virtex-6 and MIG 7 Series v1.1, DDR3 RDIM - Incorrect Column Address Width
(Xilinx Answer 42036) MIG v1.1-v1.2 DDR3 - Internal/External Vref Guidelines
General Information:
QDRII+ SRAM Memory Interface Designs
(Xilinx Answer 40578) MIG 7 Series v1.1 - Fixed latency mode is not supported for QDRII+ designs
(Xilinx Answer 40579) MIG 7 Series v1.1 - During recustomization of QDRII+ designs, the bank selection page fails to remember previous bank selection
(Xilinx Answer 40580) MIG 7 Series v1.1 - SBG324 and FBG484 packages do not have enough banks to fit x36 QDRII+ parts
(Xilinx Answer 40871) MIG 7 Series v1.1 - The minimum frequency for QDRII+ designs is 200 MHz
(Xilinx Answer 42726) MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component
(Xilinx Answer 42729) MIG 7 Series v1.1-v1.2 QDRII+ - custom x36 memory part showing the wrong data width
(Xilinx Answer 42730) MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo
AR# 40050 | |
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日期 | 08/18/2014 |
状态 | Active |
Type | 版本说明 |
器件 | |
Tools | |
IP |