2. 技术支持
  3. AR# 4017: COREGEN: What is SystemLINX?
  4. AR# 40179: SPI-4.2 v11.1 - The <core_name>_pl4_snk_top.v and <core_name>_pl4_src_top.v module declarations use incorrect port direction for AXI_SNK_ACLK and AXI_SRC_ACLK

AR# 40179

SPI-4.2 v11.1 - The _pl4_snk_top.v and _pl4_src_top.v module declarations use incorrect port direction for AXI_SNK_ACLK and AXI_SRC_ACLK

描述

In the SPI-4.2 v11.1 Core,  the <core_name>_pl4_snk_top.v and <core_name>_pl4_src_top.v files that declare the verilog modules have incorrect direction set for the AXI_SNK_ACLK and AXI_SRC_ACLK ports.

This causes errors in Synplify, but only warnings in XST (XST correctly views these as inputs despite module declaration).

解决方案

To work around this issue, the AXI_SNK_ACLK and AXI_SRC_ACLK ports should be changed from ouputs to inputs. 

This issue is scheduled to be fixed in v11.2 of the SPI-4.2 core (to be released in ISE Design Suite 13.2).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40640 SPI-4.2 v11.1 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40179
日期 05/26/2014
状态 Archive
Type 综合文章
IP