The Virtex-6 GTX Transceiver Reference Clock duty cycle specification is 45-55% as shown in Table 21 of the Virtex-6 FPGA Data Sheet for DC and Switching Characteristics.
It was 40-60% for the Virtex-5 GTX Transceiver Reference Clock.
Why is the Duty Cycle Distortion (DCD) more conservative for Virtex-6 FPGA?
If the reference clock has too much distortion, then it manifests itself as a modulation in the output of the PLL.
Most of the oscillators on the market for the SerDes-type applications have tighter Duty Cycle Distortion (DCD) specifications.