The timing issue only exists when one of the divisors for the calibration clock and the user interface clock is odd and the other one is even.
For example, a PLL divisor for the user interface clock of 2 and a divisor for the calibration clock of 11 would result in a timing error.
To work around this issue the user needs to add a synchronization register after the DONE_SOFTANDHARD_CAL register.
This will synchronize it to the memory clock domain before it can be used by the mcb_init_done_reg register.
Below are the Verilog code modifications required in the init_mem_pattern_ctr.v module to synchronize the mcb_init_done_i signal generated from the DONE_SOFTANDHARD_CAL register in the mcb_soft_calibration.v module to the clk0 clock domain.
The VHDL code modifications would similarly add two synchronization registers before the output of the DONE_SOFTANDHARD_CAL register is assigned to the mcb_init_done_reg register.
In addition, a TIG assignment should be added to the UCF to ignore the clock domain crossing path from the DONE_SOFTANDHARD_CAL register.
The UCF syntax is below for MIG 3.7 and MIG 3.61 and older.
UCF assignment for MIG 3.61 and older versions:
UCF assignment for MIG 3.7:
Original Verilog code:
New Verilog code: