AR# 40385

描述

解决方案

The timing issue only exists when one of the divisors for the calibration clock and the user interface clock is odd and the other one is even. 

For example, a PLL divisor for the user interface clock of 2 and a divisor for the calibration clock of 11 would result in a timing error. 

To work around this issue the user needs to add a synchronization register after the DONE_SOFTANDHARD_CAL register.

This will synchronize it to the memory clock domain before it can be used by the mcb_init_done_reg register. 

Below are the Verilog code modifications required in the init_mem_pattern_ctr.v module to synchronize the mcb_init_done_i signal generated from the DONE_SOFTANDHARD_CAL register in the mcb_soft_calibration.v module to the clk0 clock domain. 

The VHDL code modifications would similarly add two synchronization registers before the output of the DONE_SOFTANDHARD_CAL register is assigned to the mcb_init_done_reg register. 

In addition, a TIG assignment should be added to the UCF to ignore the clock domain crossing path from the DONE_SOFTANDHARD_CAL register.

The UCF syntax is below for MIG 3.7 and MIG 3.61 and older.

UCF assignment for MIG 3.61 and older versions:

NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;

UCF assignment for MIG 3.7:

NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;

Original Verilog code:

always @ (posedge clk_i)
begin
mcb_init_done_reg <= mcb_init_done_i;
end

New Verilog code:

//mcb_init_done_i is clocked by calibration clock
reg mcb_init_done_i_r1;
reg mcb_init_done_i_r2;

always @ (posedge clk_i)
begin
mcb_init_done_i_r1 <= mcb_init_done_i;
mcb_init_done_i_r2 <= mcb_init_done_i_r1;
mcb_init_done_reg <= mcb_init_done_i_r2;
end

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