AR# 40387


Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration


The GCLK0 pin can glitch Low when the device exits the final state of the Start-Up sequence.

The glitch does not occur if one of the following I/O Standards is used:

  • LVCMOS25 with the constraint "CONFIG VCCAUX = 3.3;"
  • LVCMOS12_JEDEC, LVCMOS15_JEDEC, LVCMOS18_JEDEC, MOBILE_DDR, or PCI33_3 without a specific "CONFIG VCCAUX" setting.


The GCLK0 pin glitch occurs when the configuration controller passes control of this pin back to the fabric. This is the only global clock pin affected because the GCLK0 pin can be used by the configuration controller as the external configuration clock for master modes (USERCCLK).

During the passing of control from the configuration controller back to the fabric, the voltage rail driver in the I/O has to be changed if one of the above mentioned I/O Standards is not used.During the transition of the voltage rail driver, if the pin receives a logic high and the fabric signal dips to Vil, max., the fabric will see a glitch low until the voltage rail driver switch occurs and the logic high is restored.

To work around this issue, critical logic can be delayed or reset after configuration, or moved to another clock input.The I/O Standard can also be set to one of the above mentioned I/O Standards which does not cause the voltage rail driver to switch and eliminates the glitch.



Answer Number 问答标题 问题版本 已解决问题的版本
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
40000 Spartan-6 - 13.4 Known Issues Related to Spartan-6 FPGA N/A N/A
AR# 40387
日期 05/20/2012
状态 Active
Type 设计咨询
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