UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40426

MIG 7 Series v1.1 - Unrequested Reads are seen in simulation immediately after calibration completes

描述

When I run a MIG v1.1 Kintex-7 or Virtex-7 DDR3 SDRAM simulation, a series of unrequested reads (~2us) are seen after calibration completes (assertion of calib_complete). 

Why are these reads sent, and do they cause any issues?

解决方案

The extra reads seen after calibration completes are expected behavior.

The calibration read leveling logic mistakenly issues the reads because the rdlvl_stg1_done signals are not asserted in time to stop the calibration logic from issuing additional reads.

These reads can be ignored.

They do not affect the functionality of calibration or user requested commands.

The code is to be modified in 7 Series MIG 1.2 (to be released with ISE Design Suite 13.2) to ensure that these reads do not occur. 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40426
日期 08/12/2014
状态 Active
Type 综合文章
器件
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 13.1
IP
  • MIG
的页面