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  3. AR# 40428: MIG 7 Series v1.1 - Guidelines for moving pins within a selected byte group

AR# 40428

MIG 7 Series v1.1 - Guidelines for moving pins within a selected byte group

描述

The MIG 7 Series tool allows users to select specific Byte Groups within an FPGA Bank for Data and Address/Control groups.The tool does not allow users to select the specific pins within those byte groups. If the pin-out generated by MIG does not follow the desired pin-out on my board, how can the design be modified?

Starting with MIG 7 Series 1.2 (available with ISE 13.2), the tools include the Verify UCF and Update Design and UCF feature. This feature allows users to input a UCF with the desired pin-out and have MIG generate the appropriate design and UCF files.

For MIG 7 Series 1.1, users need to ensure that the correct Byte Group assignments are made in the MIG generated design. From there, this Answer Record details the steps to move pins within a byte group. For example, the data group associated with DQS[0] must be assigned to the appropriate Byte Group TX within the tool. This Answer Record shows the manual changes required to swap DQ[0] with DQ[7] (as an example) in the generated design.

解决方案

Moving pins within the same I/O byte lanes in most cases involves:
(1) Changing the pin LOC constraints in the UCF file to reflect the updated pin-out
(2) Running the PARTGEN utility to generate a reference package file for the target device
(3) Changing top-level RTL parameters to reflect the new pin-out.
In some cases specifically moving CKE, ODT, and RESET_N outputs within the same bank, RTL changes are not required, and the rest of this Answer Record can be skipped.

What is an I/O Byte Lane?
An I/O Byte Lane is a group of up to 12 I/Os in the same bank that share Phaser resources specifically sharing the PHASER_OUT, PHASER_IN, OUT_FIFO, and IN_FIFO. The byte lane of any given pin is indicated by the pin name, as shown in either in a PARTGEN-generated package file or FPGA_EDITOR. The "T*" indicates which of the four byte lanes in a bank that particular pin belongs to. For example, the following is from the package file for the XC7K325FFG800 device:
#
#
 Pad
Name 		Pin
Name

vref
bank
vcco
bank
function
name
 nearest
CLB
diff
pair
tracelength
(um)
pin IOB_X0Y38 AA20
12 12 IO_L6P_T0_12 N/A 5M N/A
pin IOB_X0Y37 AB20
12 12 IO_L6N_T0_VREF_12 N/A
 5S
 N/A
pin IOB_X0Y36 AB24
12 12 IO_L7P_T1_12
N/A
 6M
N/A
pin IOB_X0Y35 AC25
12 12 IO_L7N_T1_12 N/A
6S
N/A

The above PARTGEN output shows that pins AA20 and AB20 belong to byte lane "T0" on Bank 12 (note that pin AB20 is also a possible VREF site), and that pins AB24, and AC25 belong to byte lane "T1" on Bank 12.

I/O byte lanes are used for both DDR3 data (DQ, DQS, and DM) and address/control (e.g. ADDR, RAS_N, and CAS_N). However, a given byte lane can only support either data or control/address signals, it cannot support both.

Restrictions
1. Each DDR3 I/O can only be moved within the same I/O byte lane that they it has been assigned to by the MIG tool. Note that the MIG tool does allow the user to specify the exact I/O byte lane used for each DQS group, and also provides some flexibility in which byte lanes are used for the address/control outputs.
2. DQS_P and DQS_N pin swapping (from the MIG-generated pin-out) within the same I/O byte lane is not allowed. This is because only a dedicated pair of locations within each byte lane can support DQS_P and DQS_N.
3. For the same reason, CK_P and CK_N pin swapping within the same I/O byte lane is also not allowed.
4. If internal VREF is not enabled, locations within certain byte lanes are not usable as I/O sites because they are used to provide the VREF reference voltage for that I/O bank.

Moving DDR3 I/O within the same byte lane:
1. Run the PARTGEN utility to generate package file for target device
partgen v <part_number>

2. Locate the top-level RTL parameters that will need to be changed. Refer to the table below to determine which RTL parameter(s) will have to be changed these *_MAP parameters are used by the RTL to connect the DDR3 I/O with both the appropriate PHASER blocks, and the appropriate bit lanes within these PHASER blocks.

Each RTL parameter consists of one or more 12-bit (3 hexadecimal digit) entries. MAP parameters correspond to vectored signals (e.g. ddr3_addr, ddr3_dq, ddr3_dm), each 12-bit entry corresponds to a different element in that vector for example, DATA0_MAP[11:0] corresponds to the pin location of signal ddr3_data[0], and ADDR_MAP[35:24] corresponds to the pin location of ddr3_addr[2]. Depending on the size of the DDR3 control/address and data buses, some entries within certain MAP parameters, or entire MAP parameters altogether, may not be used (e.g. for a 16-bit data bus, among the DATA*_MAP parameters, only DATA0_MAP and DATA1_MAP will be used)


In the PARTGEN-generated package file, locate the line corresponding to the pin that the target pin will be moving to. For example, we are moving ddr3_data from F30 to H26 in an XC7K325FFG800, then refer to the line:
#
# 		pad
name
 pin
name
 vref
bank
 vcco
bank
 function
name
 nearest
CLB
 diff
pair
 tracelength
(um)
pin IOB_X0Y204
H26
16
16
IO_L23P_T3_16
N.A.
118M
N/A

4. Note the Y-coordinate of the new pin location. In the above example, it is "Y204".
5. Divide the Y-coordinate by 50 and retain the remainder. This is then the relative Y-offset of the new I/O location within the I/O bank. In the above example, the Y-offset is "4".
6. Determine whether the I/O bank is a full 50-pin bank (usually the case), or a 37-pin bank.
7. Using the Bank Y-offset of the new I/O location and the appropriate table below (first table is for a 50-pin bank and second table is for a 35-pin bank), locate the corresponding Bit Lane Index (column 4). The tables below also show which pins in each bank can and cannot be used for DQ/DM and control/address. In the above example, the bit lane index corresponding to site H26 is "3" (Bank Y-Offset = 4, Byte Designator = T3).

50-pin Bank
50-pin Bank





8. Locate the entry in the appropriate MAP parameter that corresponds to the target pin, and substitute the new bit lane index to bits [3:0] of that entry leave all other bits in that entry unchanged. In the above example where ddr3_data[0] is moved from F30 to H26, DATA0_MAP would be changed from (bits[11:8]varies depending on size of the interface, and number of I/O banks used by the customer the values shown here are for illustrative purposed) "004" to "003".
9. Repeat for each pin that needs to be moved to a different location.
10. Note that the complete 12-bit entry in each MAP parameter is defined as:


As noted, moving a DDR3 I/O to a different Bank or Byte Lane is possible, and would involve change bits [11:4] of the appropriate MAP parameter entries. The MIG tool must be used to make any bank and byte changes. Manual modification is not supported.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40428
日期 02/12/2013
状态 Active
Type 综合文章
器件
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IP
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