AR# 40430: 12.4 EDK - AXI IP reset signal is not identified correctly in the CIP Wizard
AR# 40430
12.4 EDK - AXI IP reset signal is not identified correctly in the CIP Wizard
描述
When I import the AXI slave HDL during my Create and Import Peripheral Wizard session, I expect "SIGIS = RST" to be automatically provided for S_AXI_ARESETN in the MPD file.
解决方案
To work around this problem, you can manually set the reset port's attributes.
In this case, at [Port Attributes] phase in CIP Wizard, select [- List All Ports -], select S_AXI_ARESETN, add check [Display advanced attribute], then you can set [Signal Classification] to [Reset signal].