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M1.4 CPLD Hitop - Incorrect logic generated.
Customer doing an VHDL design with the following equations:
RST <= not RST_N;
RST_N <= reset_in_n and watchdog_rst_n;
In the functional simulation, the logic is correct.
After running the design through the core tools the fitter report shows the equation to be:
/RST = reset_in_n * watchdog_rst_n
/RST_N = reset_in_n * watchdog_rst_n
The signal is incorrect and the customer verified it by doing a timing simulation. It appears that the fitter is inverting the signal twice.
Please see the readme.txt for command lines used.