When I attempt to open a CORE Generator project which contains a Virtex-6 PCIe Block with location set to X0Y0&X0Y1, the following errors occur:
"ERROR:coreutil:648 - Unable to create design from file '[project path]/coregen.cgc'
ERROR:coreutil:648 - Unable to create design from file '[project path]'
ERROR:sim:722 - Unable to open project '[project path]/coregen.cgc'
ERROR:encore:268 - Project [project path]/coregen.cgc could not be opened"
The CORE Generator software is having a problem parsing the ".xco" file with the X0Y0&X0Y1 block location.
When theCORE Generator software is in debug mode, the additional message below is shown:
"Message: Unterminated entity reference, '_X0Y1'
DEBUG[repository] - Failed to parse file /[project path]/coregen.cgc"
To work around this problem, perform one of the following:
This issue has been fixed in ISE Design Suite 13.2.