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AR# 40491

13.1 CORE Generator - I receive "coreutil:648" errors when I attempt to open a project with Virtex-6 PCIe Block with location set to X0Y0&X0Y1


When I attempt to open a CORE Generator project which contains a Virtex-6 PCIe Block with location set to X0Y0&X0Y1, the following errors occur:

"ERROR:coreutil:648 - Unable to create design from file '[project path]/coregen.cgc'
ERROR:coreutil:648 - Unable to create design from file '[project path]'
ERROR:sim:722 - Unable to open project '[project path]/coregen.cgc'
ERROR:encore:268 - Project [project path]/coregen.cgc could not be opened"


The CORE Generator software is having a problem parsing the ".xco" file with the X0Y0&X0Y1 block location.

When theCORE Generator software is in debug mode, the additional message below is shown:

"Message: Unterminated entity reference, '_X0Y1'
Line: 71
DEBUG[repository] - Failed to parse file /[project path]/coregen.cgc"

To work around this problem, perform one of the following:

  • Temporarily remove the Virtex-6 PCIe Core from the project directory while editing and generating other IP cores.
  • To edit the Virtex-6 PCIe core, open the .xco file in a text editor and change "X0Y0&X0Y1" to "X0Y0" (or another valid value). Open the core customization GUI to make the desired changes, and change the block location back to X0Y0&X0Y1 before regenerating the core.

This issue has been fixed in ISE Design Suite 13.2.



Answer Number 问答标题 问题版本 已解决问题的版本
40476 13.1 CORE Generator - "ERROR:coreutil:646 - Unable to create design from file \coregen.cgc'" N/A N/A
AR# 40491
日期 05/19/2012
状态 Archive
Type 已知问题
  • ISE Design Suite - 12.1
  • ISE Design Suite - 13.1