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AR# 40492

14.x Virtex-7 - Design does not meet timing on Virtex-7 while design meets timing on Virtex-6 device

描述

I have a design that does not meet timing in a Virtex-7 device while the same design does meet timing on a Virtex-6 device.

How can I meet timing on the Virtex-7 device.

解决方案

You cannot compare apples to apples between a Virtex-6 and Virtex-7 devices. They will have completely different timing numbers.

Virtex-7 FPGAis not in production and so the timing numbers will change.

In this case, by running some smartxplorer runs, we were able to find a run that actually met timing on the Virtex-7 device.
AR# 40492
日期 05/16/2012
状态 Active
Type 设计咨询
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less
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