AR# 40493


13.x CORE Generator - Known Issues


This Answer Record contains a list of known issues involvingthe CORE Generatorsoftware in the 13.x ISE Design Suiterelease(s).

For IP-specific information, see the Xilinx IP Web page:


Outstanding Known Issues in ISE DesignSuite 13.4

(Xilinx Answer 20780) - CORE Generator - "ERROR:coreutil:195 - Could not create Java virtual machine"
(Xilinx Answer 21955) - An error occurred while running Java (possibly due to memory limitations)
(Xilinx Answer 24389) - The tab outlines of the IP views (View by function/name/Generated) are not visible on Windows XP 64-bit
(Xilinx Answer 32251) -"ERROR:coreutil:424" and "ERROR:sim:57" when using network drive
(Xilinx Answer 32320) - Issues can occur when generating/regenerating a MIG project with the same component name
(Xilinx Answer 32412) - Error message displays when customizing IP over Xwin32"X, " Error: BadWindow (invalid Window parameter) 3"
(Xilinx Answer 35374) - "WARNING:sim:541 - Could not import file 'my_core.xco' during projectmigration."
(Xilinx Answer 40559) - Project Navigator needs to be closed and re-opened before the user IP repository changes will be seen
(Xilinx Answer 40736) - Using "Create Netlist Wrapper with IO pads" option causes some cores not to generate
(Xilinx Answer 43131) - Schematic symbol for some cores are not created or created with undesired size
(Xilinx Answer 45357) - IP from a User Repository does not appear in the IP Catalog until CORE Generator is closed and re-opened
(Xilinx Answer 45359) - Import XCO fails if the project, and XCO device family do not match
(Xilinx Answer 45386) - IP Cores fail to generate when the project is accessed through a symbolic link
(Xilinx Answer 45457) - CORE Generator does not inform user that a Padded Netlist will not be created for source code core
(Xilinx Answer 45458) - Resetting MIG IP core in PlanAhead deletes all of the MIG core files
(Xilinx Answer 45485) - Setting both Verilog and VHDL output languages to "false" results in cryptic error
(Xilinx Answer 45846) - Selecting the same device in Project Options generates a benign warning
(Xilinx Answer 45849) - Upgrading MIG core to latest version does not work
(Xilinx Answer 45851) - Error not flagged for FIR v6.2 when coefficient is not negative-symetric
(Xilinx Answer 45864) - Padded netlist generation fails for Multgen and Ethernet_Statistics cores

Known Issues resolved in ISE DesignSuite 13.2

(Xilinx Answer 32396) - Generating a core through Project Navigator causes example VHDL simulation files to be overwritten
(Xilinx Answer 32486) - Help contains outdated information on how to obtain a Full IP license
(Xilinx Answer 36680) - Entering invalid parameters in IBERT core results in cryptic error message
(Xilinx Answer 40130) - "Upgrade and regenerate" process requires two steps for some cores
(Xilinx Answer 40465) - Making repository changes with Manage IP Catalog can result in a fatal error if there is a project open in the CORE Generator tool
(Xilinx Answer 40467) - A fatal error is issued if an IP repository is added that affects cores in an open project
(Xilinx Answer 40476) - Cannot open a Spartan-3A project that has a generated DCM_SP Clocking Wizard core
(Xilinx Answer 40491) - CORE Generator cannot open a project with Virtex-6 PCIe Block if block location set to X0Y0&X0Y1
(Xilinx Answer 41999) - CORE Generator fails to open if opened using the "wincoregen.exe" or "_wincg.exe"

Known Issues resolved in ISE DesignSuite 13.3

(Xilinx Answer 45407) - AXI bus shown with multiple "data" fields in customization GUI
(Xilinx Answer 45408) - Color Correction and Color-Space cores incorrectly shown for Virtex-6 project

Known Issues resolved in ISE DesignSuite 13.4

(Xilinx Answer 38170) - Spartan-3 Single DCM Clockingcore does not associate with the correct architecture
(Xilinx Answer 40475) - IP core customization GUIs are slow to open through the PlanAhead tool
(Xilinx Answer 45850) - "Customize the IP and Generate the selected output products" omits simulation models for FIFO v6.0



Answer Number 问答标题 问题版本 已解决问题的版本
32396 13.1 CORE Generator - Generating a core through Project Navigator causes VHDL example files to be overwritten N/A N/A
AR# 40493
日期 05/22/2012
状态 Archive
Type 已知问题
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