AR# 40500


12.1 EDK - CIP Wizard Does Not Generate Verilog Examples


I am trying to generate custom peripheral using the CIP wizard. While configuring the CIP wizard,I select the option to generate stub 'user_logic' template in Verilog instead of VHDL.However, it looks that the user logic template does not generate the complete example.

Is this a known issue? What is the workaround for it at the moment?


Full Verilog examples are currently not planned for Processor Local Bus (PLB) templates. A potential workaround is to use the user logic from a VHDL generated core.
AR# 40500
日期 12/15/2012
状态 Archive
Type 综合文章
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