AR# 40512


13.x PlanAhead - Known Issues


This answer record lists the known issues for the PlanAhead tool in the ISE Design Suite 13.x releases.

Each known issue includes a link to another answer record that contains additional information on the issue.


Outstanding Known Issues in PlanAhead 13.4

(Xilinx Answer 34877) - PlanAhead tool cannot find floating PR license on a different server relative to the PlanAhead license location
(Xilinx Answer 36251) - PlanAhead toolincorrectly allows users to change the slew and drive attributes on inputs and export them to the ".ucf" file
(Xilinx Answer 38335) - PlanAhead tool fails to launch on Windows OS if PATH contains a directory with parenthesis inside double quotes
(Xilinx Answer 38711) - In I/O planning project, the PlanAhead tool cannot create I/O ports for names with wildcard
(Xilinx Answer 40619) - MIG core cannot be created if IP Catalog HDL type is set to Auto in a VHDL top level design
(Xilinx Answer 40710) - Opening a project results in an Internal Exception when there is a mapped drive on the desktop
(Xilinx Answer 41668) - DIFF_TERM is not supported as an I/O property for LVDS inputs
(Xilinx Answer 42010) - Multiple I/O properties cannot be set in one step
(Xilinx Answer 42152) - Some invalid MAP options for 7 series are selectable (but not used).
(Xilinx Answer 42470) - Interactive DRC prevents correction of pin placement error in package view
(Xilinx Answer 42656) - Some Tcl 'help' commands result in an Unexpected Error
(Xilinx Answer 42700) - "More Colors" option cannot be used on Linux 64-bit
(Xilinx Answer 42733) - Synthesis "More Option" value is not saved when defining a new Strategy via the Synthesis Settings
(Xilinx Answer 43310) - PlanAhead toolfails to launch on some Windows 64-bit systems due to Java 1.6 failure
(Xilinx Answer 43759) - PlanAhead tool does not save Bitgen options between implementation runs
(Xilinx Answer 45436) - IP Catalog shows "ERROR: IPData '<IP name>' addPart found duplicate ISE Family: aartix7"
(Xilinx Answer 45458) - Resetting 3.4 MIG IP core in PlanAhead deletes all core files
(Xilinx Answer 45465) - Removing Part Compatibility settings in I/O planning does not remove associated constraints
(Xilinx Answer 45468) - Referencing a pointer to a deleted port in Tcl, causes and Unexpected Error
(Xilinx Answer 46406) - Loading RTL issues inert "xlicmgr fails to read encrypted file: ERROR:sim:928" message for encrypted files
(Xilinx Answer 46522) - Adding EDIF source file to project fails with parsing error if the EDIF keyword in file is upper case

Known Issues Resolved in PlanAhead 13.2
(Xilinx Answer 34801) - CORE Generator dialog box launches underneath the PlanAhead tool
(Xilinx Answer 40811) - "Set up ChipScope Wizard" fails for the netlist design
(Xilinx Answer 40901) - PlanAhead tool reports incorrect utilization for Spartan-3E devices
(Xilinx Answer 40963) - TIG paths are listed under Unconstrained Paths
(Xilinx Answer 41055) - Reset Constraint gives unneeded error on EDIF Project
(Xilinx Answer 41056) - Specific Reconfigurable Partitions cannot be set to Active
(Xilinx Answer 41074) - PlanAhead tool fails to launch when installed in a path with spaces
(Xilinx Answer 41082) - IP Core customization GUI opens even after a process is canceled
(Xilinx Answer 41128) - "Ignore Location Constraints" option is incorrectly set to TRUE for imported ISE projects
(Xilinx Answer 41132) - The RM properties panel shows Blackbox for all Reconfigurable Modules
(Xilinx Answer 41134) - Timing Report, Write Results to File fails on Windows operating systems
(Xilinx Answer 41154) - Multiple UCF files are incorrectly allowed for Reconfigurable Modules
(Xilinx Answer 41157) - Attempting to remove a source file of a Reconfigurable Module causes recursive options boxes
(Xilinx Answer 41167) - Synthesis appears to hang if the XILINX environment variable is set incorrectly
(Xilinx Answer 41170) - The -include_dir option for an imported Synplify project is not used
(Xilinx Answer 41172) - PlanAhead toolis unable to save Archived project to root directory
(Xilinx Answer 41202) - Import Synplify project does not import source files
(Xilinx Answer 41247) - Data2mem failure in BitGen is not recognized by PlanAhead tool
(Xilinx Answer 41454) - PlanAhead tool does not handle carry chain swap well
(Xilinx Answer 41513) - Adding source file to a project silently fails if the file name or path contain Double byte (Unicode) characters
(Xilinx Answer 41521) - Constraints are ignored if there are syntax errors in the .ucf
(Xilinx Answer 41604) - A cryptic error given when unused ICON core control ports are tied to GND
(Xilinx Answer 41618) - SSN Predictor margin not correct if run on 32-bit Windows
(Xilinx Answer 41720) - Elaborate HDL Design errors when importing a MIG design
(Xilinx Answer 41753) - INIT values specified in EDIF are ignored if specified as a hexadecimal string (e.g. 0X002F).
(Xilinx Answer 41815) - PlanAhead tool is unable to handle the routethrough through an OLOGIC element
(Xilinx Answer 42039) - Pblocks are not hi-lighted properly in PlanAhead
(Xilinx Answer 42041) - ChipScope match_units property value is not saved
(Xilinx Answer 42078) - PlanAhead tool does not open on RHEL 5.6 platform
(Xilinx Answer 42114) - Fatal Error in design runs for PR project if design is open during changes
(Xilinx Answer 42151) - Timing report shows the failing path with a skew in ms instead of ns
(Xilinx Answer 42248) - Importing Place & Route results gives an "Unexpected Error" on specific designs
(Xilinx Answer 42471) - Virtual Power/GND pins incorrectly reduce SSN Margin
(Xilinx Answer 42473) - Timing Parameter delay name cross-probing is not available for 7 series
(Xilinx Answer 42475) - DIFF_HSTL_I_DCI outputs missing rule/data to catch illegal placement in HR bank
(Xilinx Answer 42669) - Large text files cannot be edited within PlanAhead
(Xilinx Answer 42680) - PlanAhead tool allows an NCF file to be classified as a UCF file, resulting in parsing error
(Xilinx Answer 42696) - Setting Loop Count with a very large value displays unexpected results
(Xilinx Answer 42710) - Running synthesis in Tcl with the -copy_sources does not copy the include files causing synthesis to fail
(Xilinx Answer 42714) - Designs using "Global Include" files unable to be properly compiled using "Auto-Top" functionality
(Xilinx Answer 43400) - The default Vccaux for Spartan-6 devices is incorrectly set to 3.3V

Known Issues Resolved in PlanAhead 13.3

(Xilinx Answer 41101) - PlanAhead tool does not add netlists from Macro Search Path when importing .xise project
(Xilinx Answer 41166) - PlanAhead tool does not support relative directory paths in the VERILOG_DIR path variable
(Xilinx Answer 41754) - CLOCK_DEDICATED_ROUTE constraint using internal notation is altered; results in Place error:1205
(Xilinx Answer 42343) - 7 series DRC does not correctly handle more than oneIDELAYCTRL exists with IODELAY_GROUP attributes
(Xilinx Answer 42348) - Show connectivity does not show complete connectivity of some high fan out nets
(Xilinx Answer 42657) - PlanAhead tool gives an Application Exception instead of simple message when stating that SSN is not supported for a device
(Xilinx Answer 42694) - PlanAhead tool is not ordering source files correctly in the synthesis PRJ file
(Xilinx Answer 42698) - PlanAhead tool reads files that have been removed from EDIF project
(Xilinx Answer 42703) - DRC issues a warning about a PORTPROP property that was automatically added by XST synthesis
(Xilinx Answer 43108) - GTHE2_COMMON primitive is recognized as a black box
(Xilinx Answer 43112) - The xc7a30t device does not have a valid package combination
(Xilinx Answer 43114) - Total device resource estimation values are incorrect for 7vx1140t and 7a30t parts
(Xilinx Answer 43315) - The LOC constraint for OBUFDSin UCF cannot be read through NGDBuild
(Xilinx Answer 43378) - Automated LUT/ logic optimization results INIT string error
(Xilinx Answer 43399) - Auto Sort Config Pins dialog cannot be turned back on once a user selects "Don't show me again"
(Xilinx Answer 44263) - PlanAhead toolaborts when an invalid LANG environment variable value is set
(Xilinx Answer 45384) - Triple SDI or CIC Compiler cores generated through the PlanAhead IP catalog deliver un-needed files to synthesis
(Xilinx Answer 45413) - Customize Commands changes cannot be committed if changing run procedure
(Xilinx Answer 45466) - Hang possible when moving sources in Library view
(Xilinx Answer 45470) - "[Constraints 5] Cannot loc terminal 'my_sig_P' at site U36, Invalid site for GT's clock signal"

Known Issues Resolved in PlanAhead 13.4

(Xilinx Answer 38057) - DRC warning states that Vcco/Vccaux need to be a specific value, even when the UCF has this set
(Xilinx Answer 40475) - IP core customization GUIs are slow to open through the PlanAhead tool
(Xilinx Answer 42257) - An invalid component set disables an entire constraint
(Xilinx Answer 42609) - Error, "A disk write failure occurred" issued without reverence to which install file requires write permission
(Xilinx Answer 44873) - The path to a Custom Editor is not preserved after closing PlanAhead
(Xilinx Answer 44968) - Importing XST flow partition ncd causes NGDBUILD error
(Xilinx Answer 45052) - Netgen creates a port mismatch on distributed RAM model from Synplify generated EDIF
(Xilinx Answer 45250) - 7 series GT counts are incorrect in Netlist Resource Estimation
(Xilinx Answer 45472) - Text selected in column select mode cannot be deleted
(Xilinx Answer 45476) - 32-bit PlanAhead is limited to less than 2Gbytes of memory on 64-bit window OS
(Xilinx Answer 45475) - PlanAhead toolcannot import existing IP cores if the core version does not exist in the PlanAhead IP Catalog
(Xilinx Answer 45477) - PlanAhead tool reports no reason for failing to archive a project when the directory path is too long
(Xilinx Answer 45511) - An internal exception occurs when selecting some primitives in the Netlist view



Answer Number 问答标题 问题版本 已解决问题的版本
46898 13.2 PlanAhead - [ALGAI 0] Incorrect value '13.468000' specified for property 'CLKIN_PERIOD' (file = xxx.ngc, line = xxx) N/A N/A
AR# 40512
日期 05/20/2012
状态 Archive
Type 已知问题
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