UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40516

12.4/13.1 EDK AXI_Ethernet - AXI Ethernet hardware needs extra delays for accessing the registers after a core reset

描述

It has been observed that the AXI Ethernet hardware needs a certain amount of delay after a core reset before the core registers can be accessed.

解决方案

The driver file has been updated to insert adelay loop to wait for a few milliseconds after every core reset. This patch applies to AXI Ethernet systems in EDK 12.3, 12.4 and 13.1.

The patched driver file can be downloaded from the following location:
http://www.xilinx.com/txpatches/pub/applications/misc/ar40516_axiethernet.zip

  1. Replace the xaxiethernet.c file in the AXI Ethernet driver in the install area, <EDK_Install>\sw\XilinxProcessorIPLib\drivers\axiethernet_v1_01_awith the file in the patch.
  2. Clean the software libraries inSDK and rebuild the libraries and software application.

Thiis issue is scheduled to be fixed in the EDK 13.2 release.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34609 12.x EDK - 主要问答记录列表 N/A N/A
39843 13.x EDK - Master Answer Record N/A N/A
AR# 40516
日期 05/20/2012
状态 Active
Type 设计咨询
IP
  • AXI Ethernet
的页面