AR# 40548: 12.4 Speed Files - Why do I see hold violations when I run timing analysis targeting a faster speed grade?
12.4 Speed Files - Why do I see hold violations when I run timing analysis targeting a faster speed grade?
I have a design targeting a Virtex-5 -1 device that meets timing. Then, I run timing analysis targeting a faster -2 device, without re-implementing, and there are hold violations. This also happens when I target an even faster -3 device.
Is this expected behavior?
Can I use a faster device on my board, even with these hold issues, in this situation?
This is a known issue in the timing tools with Relative Mins that can occur on Virtex-5 devices. The timing tools are reporting the correct values for -2 and -3 analysis, but the problem is caused by the nature of how timing operates in Virtex-5 FPGA with Relative Min values. The Relative min data path has different values in -1 and -2 devices.
To get a worst case value for setup and hold, the timing tools should use a Relative min clock path for setup calculations and a Relative min data path for hold calculations.
Setup = Data Path Delay(max) - Clock Path Delay(Relative min)
Hold = Clock Path Delay(max) - Data Path Delay(Relative min)
By using the Relative min value in conjunction with the max value, the timing tools account for variations over PVT. This method of analysis can lead to a "false hold violation" when a faster speed file is used for timing analysis, and not re-implemented, but guarantees that the worst case analysis is preformed.
Yes, you can use a faster speed grade component on the board in place of a slower speed grade component.
This "false hold" issue does not occur in Virtex-6 and Spartan-6 devices as now the tools use Quad Timing for analysis.