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AR# 40562

12.x/13.x iMPACT - Virtex-6 - Indirect BPI core upper address bits clash with Vref pins

描述

The iMPACT Indirect BPI programming core upper address bits are dual mode and hence are also Vref pins for the bank.

These upper address bits are always driven by the core design even when target flash does not use all the Address pins. 

Vref, when used, can be driven by a power source, so contention may occur while the address lines drive low.

解决方案

You may see this on the smaller LX devices where you can use a smaller flash:

FG(G)484 Package - LX25, LX45, LX75, LX100, and LX150:

IO_L1N_A24_VREF_1_B20

CSG225 Package - LX9 and LX16:

IO_L1N_A24_VREF_1_B15

FT(G)256 Package - LX9, LX16, and LX25:

IO_L1N_A24_VREF_1 _E12

Vref should not be used for configuration banks on Virtex-6 FPGA if using Indirect BPI programming.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40503 13.x iMPACT - Known Issues for the iMPACT 13.x Software N/A N/A
AR# 40562
日期 09/05/2017
状态 Active
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • Less
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