The iMPACT Indirect BPI programming core upper address bits are dual mode and hence are also Vref pins for the bank.
These upper address bits are always driven by the core design even when target flash does not use all the Address pins.
Vref, when used, can be driven by a power source, so contention may occur while the address lines drive low.
You may see this on the smaller LX devices where you can use a smaller flash:
FG(G)484 Package - LX25, LX45, LX75, LX100, and LX150:
CSG225 Package - LX9 and LX16:
FT(G)256 Package - LX9, LX16, and LX25:
Vref should not be used for configuration banks on Virtex-6 FPGA if using Indirect BPI programming.