UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 万物智能.
  2. 技术支持
  3. AR# 4060: M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect.

AR# 4060

M1.4 Map - Map creates TIMEGRPs in PCF file that are incorrect.

描述


A design was created with two timegroups (PCI_CLK and DSP_CLK)
each with aperiod timespec assigned to them. The resulting .pcf
has several BELs have incorrectly been put into both timegroups.

解决方案

This problem has been corrected in the latest Core Tools Update:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip
AR# 4060
日期 04/03/2000
状态 Archive
Type 综合文章
的页面