AR# 40603


MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines


The 7 Series FPGA MIG DDR2/DDR3 design has two clock inputs, the reference clock and the system clock. 

The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks that are used to clock the internal logic, the frequency reference clocks to the phasers, and a synchronization pulse required for keeping PHY control blocks synchronized in multi-I/O bank implementations. 

This answer record details the MIG 7 series FPGA clocking guidelines.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)

The Xilinx MIG Solution Center is available to address all questions related to MIG. 

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


General Information

For full details on the required I/O clocks, PLL clocking structure (see the "Clocking Architecture" figure), and the guidelines for changing the input clock frequency while ensuring jitter is minimized, see the "Clocking Architecture" section in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).

The MIG tool (starting with MIG v1.2) allows users to input the Memory Clock Period and then lists available Input Clock Periods that follow the supported clocking guidelines.

Based on these two clock periods selections, the generated MIG core appropriately sets the PLL parameters.

Input Clock Guidelines

  • PLL Guidelines
    • CLKFBOUT_MULT_F (M) must be between 1 and 16 inclusive.
    • DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2 parameter.
    • CLKOUT1_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4 for below 400 MHz operation.
    • The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is met.
      For specifications, see the appropriate DC and Switching Characteristics Data Sheet.
      The 7 Series FPGAs Clocking Resources User Guide (UG472) includes the equation for calculating FVCO.
    • The relationship between the input period and the memory period is InputPeriod = (MemoryPeriod*M)/(D*D1).
    • The allowed input jitter for the input clock must meet the PLL_Finjitter spec.
      See the appropriate DC and Switching Characteristics Data Sheet.
  • The clock input (sys_clk) can now be input on any CCIO in the column where the memory interface is located.
    This includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface.
    The PLL must be located in the bank containing the clock sent to the memory.
    To route the input clock to the memory interface PLL, the CMT backbone must be used.
    With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose.

    • MIG 1.4, released with ISE Design Suite 13.4, allows this input clocking set-up and properly drives the CMT backbone.
    • The CLOCK_DEDICATED_ROUTE = BACKBONE constraint is used to implement CMT backbone. The following warning message is expected and can be ignored safely.

WARNING: [Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. The flow will continue as the CLOCK_DEDICATED_ROUTE constraint is set to BACKBONE.

u_mig_7series_0/c0_u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X0Y176
u_mig_7series_0/c0_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X0Y1
u_mig_7series_0/c1_u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X0Y5

  • For DDR3 interfaces that have the memory system input clock (sys_clk) placed on CCIO pins within one of the memory banks, MIG assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins.
    Because the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source may be connected directly to the DIFF_SSTL15 CCIO pins.
    See the below note for conditions.
  • It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs).
    However, the following criteria must be met:
    1. The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value).
      Note: This might require manually changing the DIFF_TERM parameter located in the top-level module or setting this in the UCF.
    2. The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.
    3. The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet.

      One way to accomplish the above criteria is to use an external circuit that both AC-couples and DC-biases the input signals.
      The below figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input.
      RDIFF provides the 100ohm differential receiver termination because the internal DIFF_TERM is set to FALSE.
      To maximize the input noise margin, all RBIAS resistors should be the same value, essentially creating a VICM level of VCCO/2.
      Resistors in the 10k-100K ohm range are recommended.
      The typical values for the AC coupling capacitors CAC are in the range of 100 nF.
      All components should be placed physically close to the FPGA inputs.


1) The last set of guidelines on differential LVDS inputs will be added within the LVDS and LVDS_25 (Low Voltage Differential Signaling) section of the 7 Series SelectIO Resources User Guide (UG471) in the next release of the document.
2) These guidelines are irrespective of Package, Column (HR/HP), or I/O Voltage.

Sharing sys_clk Between Controllers
As noted in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586), MIG 7 Series FPGA designs require sys_clk to be in the same I/O bank column as the memory interface to minimize jitter.

  • Interfaces Spanning I/O Columns
    • A single sys_clk input cannot drive memory interfaces spanning multiple I/O columns.
      The input clock input must be in the same column as the memory interface in order to drive the PLL using the CMT Backbone, which minimizes jitter.
  • Interfaces in Single I/O Column
    • If the memory interfaces are entirely contained within the same I/O column, a common sys_clk can be shared among the interfaces.
      The sys_clk can be input on any CCIO in the column where the memory interfaces are located.
      This includes CCIO in banks that do not contain the memory interfaces, but must be in the same column as the memory interfaces.
  • Interfaces in Different SLR
    • If multiple memory interfaces are in different SLRS, a common sys_clk can NOT be shared among the interface. THE CMT backbone does not cross the SLR boundary.

Information on Sync_Pulse

The MIG 7 Series DDR3/DDR2 design includes one PLL that generates the necessary design clocks.
One of these outputs is the "sync_pulse."
The sync pulse clock is 1/16 of the mem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%.
This clock is distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT and PHY_Control blocks in sync with each other.
The signal is sampled by the mem_refclk in both the PHASER_INs/_OUTs and PHY_Control blocks.
The phase, frequency, and Duty Cycle of the sync_pulse is chosen to provide the greatest setup and hold margin across PVT.


In certain designs due to clock source limitations, users would choose the no_buffer option in the MIG GUI and intend to drive system clock from different possible sources specified below


It is not possible to drive system clock from an IBUFDS_GTE2 as it does not satisfy the MIG requirement of routing the system clock on CLOCK_DEDICATED_ROUTE BACKBONE.

2. From a PLL/MMCM located in a different column

You cannot drive sys_clk_i from a PLL/MMCM that sits in different column to the MIG interface. Even with the no buffer option it is required that the system clock be driven from the same column as that of MIG by instantiating the buffer and providing necessary clock constraints.

Choosing the no buffer option in the MIG GUI means that the user will take care of buffer instantiation and system clock location at a later point in time, but MIG clocking rules should always be satisfied.

3. Sharing MMCM in multiple controller configurations -Information on Sharing BUFG Clock (phy_clk)

The MIG 7 Series DDR3 design includes an MMCM which outputs the phy_clk on a BUFG route.

It is NOT possible to share this clock amongst multiple controllers to synchronize the user interfaces.

This is not allowed because the timing from the fabric logic to the PHY Control Block must be controlled.

This is not possible when the clock is shared amongst multiple controllers.

The only option for synchronizing user interfaces amongst multiple controllers is to create an asynchronous FIFO for clock domain transfer.

For all of the three possible combinations Vivado might not generate an error or warning, but they do not come under supported clocking topology. Using them might not give you consistent and reliable results across PVTs.

Revision History

04/20/15Added sharing clock for multiple SLRs
09/30/13Added link to 53249
06/28/12Added information on sharing phy_clk
06/27/12Added additional information on Sync Pulse
06/05/12Added information on differential LVDS clock inputs
03/20/12Added information on sys_clk I/O standard
03/06/12Added information on Sync Pulse
02/22/12Modified Interfaces Spanning I/O Columns section
01/31/12Combined all clocking information in this Answer Record (obsolete Answer Record 41587)
11/30/11Updated to include latest clocking guidelines and tool updates
08/15/11Updated CLKFBOUT_MULT_F (M) Guidelines
05/11/11Included updated PLL settings
05/24/11Included VCO information





AR# 40603
日期 09/14/2016
状态 Active
Type 解决方案中心
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