AR# 40619


13.4 PlanAhead - MIG core cannot be created if the IP Catalog HDL type is set to Auto in a VHDL top-level design


I am trying to generate a MIG DDR3 core in the PlanAhead tool and instantiate it into a VHDL top-level design. 

However, even though the IP Catalog HDL type is set to Auto, MIG does not open and the following error occurs:

The Design Entry field in the project settings are not supported by MIG. Using Verilog for Design Entry. You need to make this change in Xilinx Core Generator project setting.

Why does this occur?


MIG 3.3 does not support VHDL. 

However, as the IP Catalog HDL type is set to Auto, even though the top-level RTL source is VHDL, MIG should still be able to output a Verilog version of the design so that it can be instantiated in the VHDL top-level in the PlanAhead tool.

To work around this issue, set the IP Catalog HDL type to Verilog (instead of Auto) to create the MIG IP core.

AR# 40619
日期 08/11/2014
状态 Archive
Type 综合文章
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