AR# 40626: Spartan-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model
AR# 40626
Spartan-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model
描述
Version Found: 1.1; v2.1 Version Resolved and other Known Issues: See (Xilinx Answer 45702).
When using ISE 13.1 software or later to simulate the wrapper using the provided root port model, simulation will fail with the following error message:
DRC Error : Value of POWER_SAVE[4] should be set to 1'b1 for instance board.RP.rport.pcie_2_0_i.pcie_gt_i.gtx_v6_i.GTXD[0].GTX of GTXE1.
解决方案
This error is caused by the Virtex-6 FPGA Root Port model that is used in simulation with the Spartan-6 FPGA endpoint wrapper. To fix this, edit the file gtx_wrapper_v6.v[hd]. This file is found in the core's generated directory: <core_name>/simulation/dsport
For Verilog change:
.POWER_SAVE(10'bxxxx10xxxx),
To
.POWER_SAVE(10'bxxxx11xxxx),
For VHDL change:
POWER_SAVE => "xxxx10xxxx",
To:
POWER_SAVE => "xxxx11xxxx",
Revision History 01/18/2012 - Updated; added reference to 45072 03/01/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.