AR# 40640: SPI-4.2 v11.1 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.1
AR# 40640
SPI-4.2 v11.1 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.1
描述
This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v11.1 Core (released in ISE Design Suite13.1), and contains the following information:
(Xilinx Answer 32917) - Virtex-6 FPGA change to HIGH_PERFORMANCE_MODE attribute for IODELAYE1 elements in UCF
If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the Multiple Core Instantiation section in the Special Design Considerations chapter of the LogiCORE IP SPI-4.2 v10.4 User Guide.
(Xilinx Answer 15500) - How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
(Xilinx Answer 16112) - LogiCORE SPI-4.2 (POS-PHY L4) - What is the ideal DCM phase shift value for SPI-4.2 (PL4) static alignment clock (RDClk)?
Known Issues
(Xilinx Answer 40823) - SPI-4.2 - Updated Sink Core performance and MMCM settings for using Global Clocking on Virtex-6 devices
(Xilinx Answer 41130) - SPI-4.2 - Updated Source Core MMCM settings for using Global Clocking at 1G on Virtex-6 devices
(Xilinx Answer 41200) - SPI-4.2 - Updated Virtex-7 device Sink Core performance and Virtex-7 and Kintex-7 Sink and Source Core MMCM settings for using Global Clocking
(Xilinx Answer 41201) - LogiCORE IP SPI-4.2 v11.1 - Can LVTTL be used for Virtex-7 and Kintex-7 Status I/O?
(Xilinx Answer 40178) - SPI-4.2 v10.4 and v11.1 - DPA diagnostic port SnkDPARamValid does not assert correctly for Virtex-6, Virtex-7 and Kintex-7 devices
(Xilinx Answer 40179) - SPI-4.2 v11.1 - The <core_name>_pl4_snk_top.v and <core_name>_pl4_src_top.v module declarations use incorrect port direction for AXI_SNK_ACLK and AXI_SRC_ACLK
(Xilinx Answer 40180) - SPI-4.2 v11.1 - 7 Series timing simulations might report HOLD violations on various blocks within the design (e.g. X_RAMB18E1, X_FF, X_RAMD64, etc.).
(Xilinx Answer 40181) - SPI-4.2 v11.1 - 7 Series core functional and timing simulations might fail to complete DPA due to X propagation from ISERDES
(Xilinx Answer 40875) - SPI-4.2 v11.1 - Incorrect Side Band Error signal could be asserted in Transparent Status Mode
(Xilinx Answer 40569) - SPI-4.2 v11.1 - Dynamic Phase Alignment may sometimes fail when targeting Kintex-7 or Virtex-7 FPGAs
(Xilinx Answer 41711) - SPI-4.2 v10.4 and v11.1 - Dynamic Phase Alignment might fail when using "Sink DPA Clock Adjust" and targeting a Virtex-6 FPGA
(Xilinx Answer 42758) - SPI-4.2 v11.1 and v11.2 (AXI) - Using HR I/O when targetting Virtex-7 and Kintex-7 devices
Constraints and Implementation Issues
(Xilinx Answer 40841) - SPI-4.2 v11.1 - When implementing a SPI-4.2 design through NGDBuild, MAP, PAR and BitGen, several "WARNING" messages appear
General Simulation Issues
(Xilinx Answer 21321) - Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;
(Xilinx Answer 20030) - When I simulate an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation