We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40666

Project Navigator - Can I add my company and engineer name for automatically generated files?


Whenever a new VHDL, Verilog, or Testbench file is created, few information is given, as shownbelow. Iwant the values in the generated files to be automatically populated with my company and user-specific data.

Can this be done?

-- Company:
-- Engineer:
-- Create Date: 15:45:47 02/10/2011
-- Design Name:
-- Module Name: delete - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:


No, Project Navigator does not have a way to pull in user-specific data for these generated files.

You can hard code some of your own data for three of the generated templates using the following files:

%XILINX%\ISE\data\projnav\scripts\dpm_sourceTasks.Tcl, line 713- VHDL Module

%XILINX%\ISE\data\testbnch2.tcl- VHDL Testbench

%XILINX%\ISE\data\projnav\scripts\dpm_sourceTasks.Tcl, line 622- Verilog module

AR# 40666
日期 12/15/2012
状态 Active
Type 综合文章
  • 1700/E/D/L