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AR# 40707

Virtex-6 Integrated Blcok Wrapper v2.2 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt


Known Issue: v2.1, v1.4, v1.3, v1.2, v1.1

When generating a Legacy Interrupt, the Virtex-6 Integrated Block Wrapper does not set the Interrupt Status bit within the Status Register of the configuration space.


The interrupt status bit is bit 3 of the Status Register, located at Offset 06H in the Endpoint's Type0 configuration space.

This bit should be set when a legacy interrupt is generated to indicate that an interrupt is pending internally in the device.

The Virtex-6 Integrated Block Wrapper does not set this bit correctly when the application generates a legacy interrupt on the CFG interface.

The system software uses this bit to identify the interrupting device in the scenario where multiple interrupt vectors are collapsed upstream.

There is no work-around at this time.

However, this issue has not been known to cause any system problems for customers.

Revision History
02/16/2011 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
39353 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 N/A N/A
AR# 40707
日期 09/22/2014
状态 Active
Type 已知问题
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )