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AR# 40779

MIG Spartan-6 MCB - How to properly terminate ODT, CKE, and RESET

描述

The Memory Controller drives the ODT, CKE, and RESET signals during normal operation and LOW during initialization.

However, a pull-down with a 4.7 KOhm resistor connected to GND is still required to adhere to the DDR, DDR2 and DDR3 Memory Standards.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)

The Xilinx MIG Solution Center is available to address all questions related to MIG.

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information

解决方案

Based off of the Power-Up Initialization Sequence defined by the DDR3 Spec, RESET# is recommended to be Low right at power On. 

To guarantee this occurs while the FPGA is being configured (before it can drive RESET "Low"), the pull-down to GND is recommended. 

Based off of the Power-Up Initialization Sequence defined by the DDR2 Spec, CKE and ODT should be maintained at a LOW state while applying power.

To guarantee this occurs while the FPGA is being configured (before it can drive CKE and ODT "Low"), the pull-down to GND is required. 

Based off of the Power-Up Initialization Sequence defined by the DDR Spec, CKE should be maintained at a LOW state while applying power. 

To guarantee this occurs while the FPGA is being configured (before it can drive CKE  "Low"), the pull-down to GND is required. 

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40778 MIG Spartan-6 MCB - Termination and I/O Standard Guidelines N/A N/A
AR# 40779
日期 06/06/2014
状态 Active
Type 综合文章
器件
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
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