AR# 40787: Design Assistant for XST Help determining why an instance is black boxed
AR# 40787
Design Assistant for XST Help determining why an instance is black boxed
描述
Please refer to this answer record for help determining why an instance is black boxed.
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.
解决方案
An instance is considered black boxed when there is no RTL to describe the logic within the instance. Instead, the logic is described by a netlist. The extension to these netlists are either an NGC, NGO, EDF, or EDIF. For Xilinx, they are either created by Coregen, Synplicity, or XST in a smaller design. Most of the time it is OK to black box a component. However, occasionally this is not intended.
When XST compiles all of its modules/entities, it compiles them to specific libraries. You can see what libraries they are compiling them to by looking at the .prj file. Most of the time, modules/entities are compiled to the work library; however, this is not always the case. A module/entity will automatically look in the library that is compiled to for the component that is instantiated. For example: if module/entity A belongs to a library called, "fifo_lib" and component B is instantiated, then module/entity A will look only in library "fifo_lib" for component B. If component B is not part of library "fifo_lib", then component B will be considered a Black Box.
VHDL has the ability for an entity to look at more libraries other than its own library. There is only one exception and this is when an entity tries to use the work library when it is not already in the work library. To look into other libraries the library declaration is used. An example of a library declaration is shown below:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all;