AR# 40829

SPI-4.2 v10.4 - "ERROR:NgdBuild:604..." seen when using Synplify and targeting a Virtex-6 device

描述


When I use Synplify to target a Virtex-6 device, the following error occurs with the SPI-4.2 v10.4 example design:

"ERROR:NgdBuild:604 - logical block 'pl4_src_clk0' with type 'pl4_src_clk' could not be resolved. A pin name misspelling can cause this, a missing EDIF or NGC file, case mismatch between the block name and the EDIF or NGC file name, or the misspelling of a type name. Symbol 'pl4_src_clk' is not supported in target 'virtex6'."

解决方案


This is scheduled to be fixed in the v10.5 SPI-4.2 Core in ISE Design Suite 13.2.

In the meantime, to work around this error you can make the following changes to the generated <core_name>/implement/synplify.prj file:

1) Replace the following lines:
set_option -technology VIRTEX5
set_option -part XC5VLX50
set_option -package FF676

With the following lines:
set_option -technology VIRTEX6
set_option -part XC6VLX75T
set_option -package FF784


2) For VHDL designs, replace the following line:
add_file -vhdl -lib work "../example_design/pl4_snk_clk.vhd"

With the following lines:
add_file -vhdl -lib work "../example_design/pl4_snk_clk.vhd"
add_file -vhdl -lib work "../example_design/pl4_src_clk.vhd"


3) For Verilog designs, remove the following line:
add_file -verilog "../example_design/virtex5.v"


4) For Verilog designs, replace the following line:
add_file -verilog "../example_design/pl4_snk_clk.v"

With the following lines:
add_file -verilog "../example_design/pl4_snk_clk.v"
add_file -verilog "../example_design/pl4_src_clk.v"
AR# 40829
日期 02/23/2011
状态 Active
Type 综合文章
IP