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AR# 4084

Synplify - How do I disable clock buffer (BUFG) insertion?

Description

How do I disable clock buffer (BUFG) insertion?

By default, Synplify inserts global clock buffers on the clock signals with the highest fanout.

The rules for insertion are defined internally in Synplify, but typically, Synplify assigns a BUFG to any input signal that directly drives a clock.

解决方案


Use the Synplify constraints file (SDC) for passing vendor-specific attributes.

The syntax for specifying a normal buffer rather than a clock buffer resource for the clock signal is as follows:

define_attribute {input_clock_port} syn_noclockbuf 1


You can use a global specification to specify the use of normal buffers rather than clock buffers for all clock signals as follows:

define_global_attribute syn_noclockbuf 1


Verilog:

To turn off automatic clock buffers for entire modules, use the following:

module my_design (o, i, clk_in) / * synthesis syn_noclockbuf=1 */;


To turn off automatic clock buffers for specific inputs, use the following:

module my_design (o, i, clk_in) ;
output o;
input i;
input clk_in /* synthesis syn_noclockbuf=1 */;


If the clock in your design has an instantiated IBUF, you must turn off automatic clock buffers for a specific signal as follows:

:
wire clk_used /*synthesis syn_noclockbuf=1*/;
IBUF u_ibuf ( .I ( clk_input ) , .O( clk_used ) ) ;
:


VHDL:

To turn off automatic clock buffers for entire architectures, use the following:

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;

entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
end entity;

architecture Xilinx of my_design is

attribute syn_noclockbuf of Xilinx : architecture is true;


To turn off automatic clock buffers for specific inputs, use the following:

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;

entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
attribute syn_noclockbuf of clk_in : signal is true;
end entity;


If the clock port in your design has an instantiated IBUF, you must turn off automatic clock buffers for a specific signal as follows:

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;
:
:
signal clk_used : std_logic;

attribute syn_noclockbuf of clk_used : signal is true;
:
:

AR# 4084
创建日期 08/21/2007
Last Updated 06/10/2015
状态 Active
Type 综合文章
Tools
  • ISE Design Suite
  • Vivado Design Suite