Description

How do I disable clock buffer (BUFG) insertion?

By default, Synplify inserts global clock buffers on the clock signals with the highest fanout.

The rules for insertion are defined internally in Synplify, but typically, Synplify assigns a BUFG to any input signal that directly drives a clock.

解决方案

define_attribute {input_clock_port} syn_noclockbuf 1

define_global_attribute syn_noclockbuf 1

module my_design (o, i, clk_in) / * synthesis syn_noclockbuf=1 */;

module my_design (o, i, clk_in) ;
output o;
input i;
input clk_in /* synthesis syn_noclockbuf=1 */;

:
wire clk_used /*synthesis syn_noclockbuf=1*/;
IBUF u_ibuf ( .I ( clk_input ) , .O( clk_used ) ) ;
:

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;

entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
end entity;

architecture Xilinx of my_design is

attribute syn_noclockbuf of Xilinx : architecture is true;

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;

entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
attribute syn_noclockbuf of clk_in : signal is true;
end entity;

library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;
:
:
signal clk_used : std_logic;

attribute syn_noclockbuf of clk_used : signal is true;
:
: