We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4085

M1.x: Is there a way to access vertical longlines in FPGA (with ucf or pcf constraint)?


General Description:

There is no specific constraint that will force the

use of a particular routing resource, unless you make a

hard macro.


Here are some possibilites:

1) Use timespecs

2) Align logic using given signal into column (using RLOCs/LOCs). This

will encourage use of vertical longlines.

3) Use PCF constraint: NET my_net PRIORITIZE = 90;

This, along with timespec, will encorage use of longlines.

4) Modify the design in EPIC to use longlines.

AR# 4085
日期 01/18/2010
状态 Archive
Type 综合文章