A critical step in verifying board layout guidelines for memory interface designs includes using IBIS to run signal integrity simulations. Remember to run these simulations for both pre-board layout and post-board layout. These simulations confirm the signal integrity on the board.
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The ML561 Hardware-Simulation Correlation chapter of the Virtex-5 FPGA ML561 Memory Interfaces Development Board User Guide (UG199) can be used as a guideline. This chapter provides a detailed look at signal integrity correlation results for the ML561 board, and can be used as an example for what to look at and what you should see. It also provides the steps to create a design-specific IBIS model to aid in setting up the simulations.
(Xilinx Answer 37081)MIG Spartan-6 MCB - Calibrated Input Termination IBIS Simulation