2. 技术支持
  3. AR# 4089: How to simulate Exemplar written VHDL in MTI or QuickHDL. Post synthesis pre NGDBuild
  4. AR# 40897: LogiCORE IP - X's are seen in ModelSim 6.6c functional or timing simulation

AR# 40897

LogiCORE IP - X's are seen in ModelSim 6.6c functional or timing simulation

描述

In ModelSim 6.6c, X's are seen in functional or timing simulation, and simulation fails to complete successfully.

解决方案

There is a known issue in ModelSim 6.6c that is scheduled to be fixed in ModelSim 6.6e. 

This issue can be worked around in ModelSim 6.6c in the following ways:

  • When all the signals are dumped in the waveform (add list -r *)
  • When all signals are logged by the simulator without displaying any extra signals in the waveform window (add log -r *)
AR# 40897
日期 09/08/2014
状态 Active
Type 综合文章
IP