AR# 40955: LogiCORE IP Ethernet AVB Endpoint v3.1 - Timing Simulation occasionally times out
LogiCORE IP Ethernet AVB Endpoint v3.1 - Timing Simulation occasionally times out
Timing Simulation of the example design occasionally times out for the Ethernet AVB Endpoint v3.1 core:
Loading work.glbl(fast) # Loading instances from ../../implement/results/routed.sdf # Loading timing data from ../../implement/results/routed.sdf # ** Note: (vsim-3587) SDF Backannotation Successfully Completed. # Time: 0 ps Iteration: 0 Region: /demo_tb File: ../demo_tb.v # ** Warning: (vsim-3316) No solution possible for some delayed timing check nets. 27 negative limits were zeroed. Use +ntc_warn for more info. # Region: /demo_tb # 1269508320 # 0 # ** Note: Timing checks are not valid # ** Error: Testbench timed out
In temac_loopback_shim_inst/ifg_counter_0 a $recovery error is reported between the falling edge of RST (@125404ps) and the rising edge of CLK (@125940ps). This is an asynchronous reset signal input to a "pretend" Ethernet MAC module that is just in the example design to loopback the signals into the AVB design.
This timing simulation failure is caused by timing of the reset de-assertion on a module that is not intended to be used only as an example and not put in an actual design. The timing simulation can be made to pass by slightly altering when the reset is deasserted in the demo testbench.