AR# 41170

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13.1 PlanAhead - [HDLCompilers 26] "" Line # Could not find verilog include file 'xxx.vh'

描述

When I import a Synplify".prj" file into the PlanAhead tooland synthesize the design, an error is reported similar to the following:

"[HDLCompilers 26] "C:\test_proj\top.v" Line 15Could not find verilog include file 'defines.vh'"

The included file exists and is in the location specified by the -include_dir option of the ".prj" file.

What is the cause of the errorand howcan Iresolve this issue?

解决方案

PlanAhead tool 13.1 doesnotuse the-include_dir option for animported synplify ".prj" file.

To work around this issue,import thefilesof the project.Usethe Tcl command "add_files -scan_for_includes" or theProject Manager, Add Sources Wizard.

Thisissueis scheduled to befixed in ISE Design Suite 13.2.

AR# 41170
日期 12/15/2012
状态 Archive
Type 综合文章
Tools
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