AR# 4119: Orcad Express: Timed simulation for Xilinx M1 does not include global reset by default
Orcad Express: Timed simulation for Xilinx M1 does not include global reset by default
Keywords: Orcad, Express, simulation, timing, GSR, global reset
General Description: Orcad Express Timed simulation for Xilinx M1 designs does not include external interface to global reset by default
Post-route simulation netlists created by Express Build via Xilinx M1 tools will not include an external interface to global reset (GSR_PORT) unless specified by the user.
Enable the GSR port by selecting the option "Bring out global reset net as port" of the NGD2VHDL tab of the Xilinx M1 Build Settings dialog box.
GSR_PORT is an internal signal of post-route VHDL netlists created by M1. The internal high-fan out control provides global asynchronous reset to all flip-flops of the model architecture. It may be necessary to provide test bench stimulus to initialize circuits. For example:
-- Expression added to post-route test bench to pulse global reset net GSR_PORT <= '0' after 25 ns, '1' after 100 ns;