AR# 4120: Orcad Express: ROM outputs remain low in functional simulation
Orcad Express: ROM outputs remain low in functional simulation
Keywords: Orcad, simulation, functional, ROM
General Description: When trying to perform a functional simulation of a Xilinx design containing ROMs, the ROM outputs remain low, regardless of the address accessed.
In Simulate v6.0, the Convert XNF to VHDL command on the Tools menu ignores all part attributes such as ROM initialization. Xilinx ROMs are initialized in the schematic by the OPTIONS_1 property as INIT=<value>. As a workaround when using ROMs in a Xilinx design, translate the .XNF files with the Timing Simulation option selected.