|Speed Grade ||<=900Mbps||1Gbps||1.1Gbps||1.2Gbps||1.25Gbps|
|-1||Regional/Global ||Regional only* ||Regional only* ||NA||NA|
|-2||Regional/Global ||Regional/Global ||Regional/Global ||Regional Only* ||NA |
|-3||Regional/Global ||Regional/Global ||Regional/Global ||Regional/Global||Regional/Global|
*Note the Clocking schemes marked with a '*' have been updated since the SPI-4.2 v11.1 release in ISE13.1
For Virtex-7 and Kintex-7 devices, the SysClk and SnkClk MMCM bandwidth should be changed from "Optimized" to "High" to ensure low output jitter.
For a specific frequency and speed grade, it might be possible to generate more optimal MMCM settings than the default provided with the core. It is recommended that users use the latest LogiCORE Clocking Wizard IP to generate the optimum MMCM instantiation for their specific data rate; see (Xilinx Answer 39432) for step-by-step guidance on how to generate an MMCM instantiation for the SPI-4.2 core using the Clocking Wizard IP.